%0 Conference Proceedings
%T ERA: An Efficient Routing Algorithm for Power, Throughput and Latency in Network-on-Chips
%+ Computer Engineering Department
%A Sharma, Varsha
%A Agarwal, Rekha
%A Gaur, Manoj S.
%A Laxmi, Vijay
%A V., Vineetha
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B IFIP International Conference on Network and Parallel Computing (NPC)
%C Zhengzhou, China
%Y Chen Ding; Zhiyuan Shao; Ran Zheng
%I Springer
%3 Network and Parallel Computing
%V LNCS-6289
%P 481-490
%8 2010-09-13
%D 2010
%R 10.1007/978-3-642-15672-4_41
%K Network-on-Chip
%K Energy Model
%K Deterministic Routing
%K Adaptive Routing
%K Deadlock
%K Turn Model
%K Latency
%K Throughput
%Z Computer Science [cs]/Digital Libraries [cs.DL]Conference papers
%X Network-on-Chip (NoC) is viewed as a viable substitution for traditional interconnection networks to achieve high performance, communication efficiency and reliability in complex VLSI architectures at deep sub micron. Achieving high performance, power efficiency with optimum area is a target for any routing algorithm in NoC. In this paper, we propose a novel routing scheme named 'ERA', which offers higher throughput with controlled delays while remaining power aware. ERA is an adaptive routing algorithm, which avoids congestion and tends to minimize the hot spots in the network. Unlike other existing algorithms, the proposed algorithm does not require any virtual channels to avoid deadlocks. We compare our algorithm with XY and OE on the basis of a performance metric called 'power performance factor' for different traffic patterns and injection models. Our results show that ERA performs better than these two algorithms.
%G English
%2 https://inria.hal.science/hal-01054960/document
%2 https://inria.hal.science/hal-01054960/file/ERA.pdf
%L hal-01054960
%U https://inria.hal.science/hal-01054960
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-LNCS-6289
%~ IFIP-NPC
%~ IFIP-2010