@inproceedings{sharma:hal-01054960,
  TITLE = {{ERA: An Efficient Routing Algorithm for Power, Throughput and Latency in Network-on-Chips}},
  AUTHOR = {Sharma, Varsha and Agarwal, Rekha and Gaur, Manoj S. and Laxmi, Vijay and V., Vineetha},
  URL = {https://inria.hal.science/hal-01054960},
  BOOKTITLE = {{IFIP International Conference on Network and Parallel Computing (NPC)}},
  ADDRESS = {Zhengzhou, China},
  EDITOR = {Chen Ding; Zhiyuan Shao; Ran Zheng},
  PUBLISHER = {{Springer}},
  SERIES = {Network and Parallel Computing},
  VOLUME = {LNCS-6289},
  PAGES = {481-490},
  YEAR = {2010},
  MONTH = Sep,
  DOI = {10.1007/978-3-642-15672-4\_41},
  KEYWORDS = {Network-on-Chip ; Energy Model ; Deterministic Routing ; Adaptive Routing ; Deadlock ; Turn Model ; Latency ; Throughput},
  PDF = {https://inria.hal.science/hal-01054960/file/ERA.pdf},
  HAL_ID = {hal-01054960},
  HAL_VERSION = {v1},
}