%0 Conference Proceedings
%T Exposing Tunable Parameters in Multi-threaded Numerical Code
%+ Texas State University
%+ The University of Texas at San Antonio (UTSA)
%A Qasem, Apan
%A Guo, Jichi
%A Rahman, Faizur
%A Yi, Qing
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B IFIP International Conference on Network and Parallel Computing (NPC)
%C Zhengzhou, China
%Y Chen Ding; Zhiyuan Shao; Ran Zheng
%I Springer
%3 Network and Parallel Computing
%V LNCS-6289
%P 46-60
%8 2010-09-13
%D 2010
%R 10.1007/978-3-642-15672-4_6
%K Autotuning
%K memory hierarchy
%K optimization
%K parallelism
%Z Computer Science [cs]/Digital Libraries [cs.DL]Conference papers
%X Achieving high performance on today's architectures requires careful orchestration of many optimization parameters. In particular, the presence of shared-caches on multicore architectures makes it necessary to consider, in concert, issues related to both parallelism and data locality. This paper presents a systematic and extensive exploration of thecombined search space of transformation parameters that affect both parallelism and data locality in multi-threaded numerical applications.We characterize the nature of the complex interaction between blocking, problem decomposition and selection of loops for parallelism. We identify key parameters for tuning and provide an automatic mechanism for exposing these parameters to a search tool. A series of experiments on two scientific benchmarks illustrates the non-orthogonality of the transformation search space and reiterates the need for integrated transformation heuristics for achieving high-performance on current multicore architectures.
%G English
%2 https://inria.hal.science/hal-01054957/document
%2 https://inria.hal.science/hal-01054957/file/paper.pdf
%L hal-01054957
%U https://inria.hal.science/hal-01054957
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-LNCS-6289
%~ IFIP-NPC
%~ IFIP-2010