%0 Conference Proceedings
%T Physical Design Issues in 3-D Integrated Technologies
%+ LSI EPFL
%+ Department of Electrical and Computer Engineering
%A Pavlidis, Vasilis F.
%A Friedman, Eby G.
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
%C Rhodes Island, India
%Y Christian Piguet; Ricardo Reis; Dimitrios Soudris
%I Springer
%3 VLSI-SoC: Design Methodologies for SoC and SiP
%V AICT-313
%P 1-21
%8 2008-10-13
%D 2008
%R 10.1007/978-3-642-12267-5_1
%Z Computer Science [cs]/Digital Libraries [cs.DL]Conference papers
%X Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.
%G English
%2 https://inria.hal.science/hal-01054273/document
%2 https://inria.hal.science/hal-01054273/file/03130008.pdf
%L hal-01054273
%U https://inria.hal.science/hal-01054273
%~ IFIP
%~ IFIP-AICT
%~ IFIP-AICT-313
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-TC10
%~ IFIP-WG10-5
%~ IFIP-2010