Some Hardware Aspects of the BESM-6 Design - Perspectives on Soviet and Russian Computing Access content directly
Conference Papers Year : 2011

Some Hardware Aspects of the BESM-6 Design

V. I. Smirnov
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This paper very shortly describes some hardware solutions of central processor (CPU) of BESM-6. CPU had very deep instruction pipe with an associative buffer for instructions and an associative buffer for data with original protocol. Logical and storage elements used only domestic discrete components. Main logical unit based on differential amplifier with pyramid of rich diode logic and paraphase synchronization. Original construction without printed plate made wire connections very short and gave possibilities for direct access to every contacts and interchanging modules. All these solutions permitted to achieve high clock frequency, reliability and effective maintenance.
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Dates and versions

hal-01568415 , version 1 (25-07-2017)





V. I. Smirnov. Some Hardware Aspects of the BESM-6 Design. 1st Soviet and Russian Computing (SoRuCom), Jul 2006, Petrozavodsk, Russia. pp.20-25, ⟨10.1007/978-3-642-22816-2_3⟩. ⟨hal-01568415⟩
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