VLSI-SoC 2007: Atlanta, GA, USA - Selected Papers
VLSI-SoC: Advanced Topics on Systems on a Chip - A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007), October 15-17, 2007, Atlanta, USA
Springer, IFIP 291, ISBN: 978-0-387-93845-5
Contents
Gustavo Neuberger, Gilson I. Wirth, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis
1-16
Use of Gray Decoding for Implementation of Symmetric Functions.
Osnat Keren, Ilya Levin, Radomir S. Stankovic
1-16
A Programmable Multi-Dimensional Analog Radial-Basis- Function-Based Classifier.
Sheng-Yu Peng, Paul E. Hasler, David V. Anderson
1-20
Compression-based SoC Test Infrastructures.
Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre
1-15
Parametric Structure-Preserving Model Order Reduction.
Jorge Fernandez Villena, Wil H. A. Schilders, L. Miguel Silveira
1-20
ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching.
Marco Paolieri, Ivano Bonesana, Marco D. Santambrogio
1-20
QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques.
Aline Mello, Ney Calazans, Fernando Moraes
1-22
Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis.
Almitra Pradhan, Ranga Vemuri
1-20
Statistical and Numerical Approach for a Computer efficient circuit yield analysis.
Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo Reis
1-24
SWORD: A SAT like Prover Using Word Level Information.
Robert Wille, Görschwin Fey, Daniel Große, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
1-17
A new analytical approach of the impact of jitter on continuous time delta sigma converters.
Julien Goulier, E. Andre, Marc Renaudin
1-16
An adaptive genetic algorithm for dynamically reconfigurable modules allocation.
Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto
1-18
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm.
Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz
1-22
System and Procesor Design Effort Estimation.
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau
1-21
Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors.
Antonio Carlos Schneider Beck, Luigi Carro
1-16
First Order, Quasi-Static, SOI Charge Conserving Power Dissipation Model.
Sameer Sharma, L. G. Johnson
1-23