Molecular Electronics - Devices and Circuits Technology.

Paul D. Franzon, David Nackashi, Christian Amsinck, Neil Di Spigna, Sachin Sonkusale

 1-10

Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.

G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard

 11-24

A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.

Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José C. Monteiro, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis

 25-39

Defragmentation Algorithms for Partially Reconfigurable Hardware.

Markus Koester, Heiko Kalte, Mario Porrmann, Ulrich Rückert

 41-53

Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.

Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin

 55-69

3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System.

Chul Kim, A. M. Rassau, Stefan Lachowicz, Saeid Nooshabadi, Kamran Eshraghian

 71-86

Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms.

Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto

 87-109

A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.

Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici

 111-125

Issues in Model Reduction of Power Grids.

João M. S. Silva, L. Miguel Silveira

 127-144

A Traffic Injection Methodology with Support for System-Level Synchronization.

Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen

 145-161

Pareto Points in SRAM Design Using the Sleepy Stack Approach.

Jun-Cheol Park, Vincent John Mooney III

 163-177

Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.

César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis

 179-194

Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.

Jerome Quartana, Laurent Fesquet, Marc Renaudin

 195-207

A Novel MicroPhotonic Structure for Optical Header Recognition.

Muhsen Aljada, Kamal Alameh, Adam Osseiran, Khalid Al-Begain

 209-219

Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint.

Erik Larsson, Stina Edbom

 221-244

On-chip Pseudorandom Testing for Linear and Nonlinear MEMS.

Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur

 245-266

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.

Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault

 267-281

On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.

Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner

 283-297

Exact BDD Minimization for Path-Related Objective Functions.

Rüdiger Ebendt, Rolf Drechsler

 299-315

Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.

Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathebras, Gilles Sassatelli, Fernando Gehm Moraes

 317-330

A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.

Cristiano Lazzari, Lorena Anghel, Ricardo Reis

 331-344